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AMD conFusion? Forget the hype!

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From tech.icrontic.com

 

I must apologies in advance for the wall of text, however it isn't heavy reading. But is interesting to get past the hype, and finally understand just how AMD's next gen will in fact be different.

 

"You might be surprised to learn that AMD is just seven months away from releasing new CPUs based on not one, but three, new designs. The Phenom II that we have known for the past 17 months will soon be put to pasture, never to be seen again. Its replacements are built for the server, the desktop, the notebook and the netbook.

 

Dubbed Bulldozer, Bobcat and Llano, the new processor designs are the final piece of AMD’s grand strategy to emerge from years of debt and struggle as a leaner, meaner company. For enthusiasts, they are something altogether more important: a clear sign that the fascinating war between AMD and Intel is about to go nuclear once again.

 

Bulldozer: The chip for enthusiasts

Posted Image

Chips based on Bulldozer will be scalable across any number of what AMD calls “modules” (shown above), each of which contains two CPU cores. It is postulated that each module is equipped with a technology called Cluster-Based Multi-Threading, or CMT.

 

To understand CMT, we must first have an understanding of its lesser sibling, Symmetric Multi-Threading (SMT), which you are likely to know by Intel’s name: Hyper-Threading. Though Intel did not create the technology, their implementation is by far the most famous.

 

Intel’s implementation of SMT duplicates architectural states—the part of a CPU which holds the condition of a process—but not the execution engine. This allows their processors to maximize execution resources by busying silicon that would otherwise lay idle, or by injecting threads into the pipeline in the event of a stall.

 

To give a real-world analogy, Intel’s implementation of SMT is similar to an automobile assembly plant with only one assembly line capable of taking a car from parts to completion. At every stage of the assembly, however, workers are standing by with completed parts to keep the line moving if there’s a problem. The workers can’t build a car (they don’t have a line), but they can make sure that line is always moving the car on to the next step without issue.

 

Intel uses SMT in the same way: to ensure that the processor’s line is always busy moving to the next step, and today’s operating systems are increasingly intelligent at dispatching threads for this setup.

 

The “problem” with this implementation of SMT is that one instruction window tracks the dispatch, execution and retirement of both threads. Going back to the assembly line, it would be like putting one supervisor in charge of watching the line and the workers—that supervisor can’t watch for problems with the line and the workers at the same time. Something is bound to fail. On a CPU, as in an assembly line, failures lead to a reduction in apparent performance.

 

Each Bulldozer module, meanwhile, puts the plant on steroids not only by adding a second fully-functional assembly line, but by giving each line the ability to break one big stage down into several, parallel stages—little assembly lines that can be created, run, merged and closed on demand without sacrificing the efficiency of the main assembly line. This is CMT, and the Bulldozer can do it.

Posted Image

 

CMT is more efficient and performs more consistently than Hyper-Threading.

 

When a processor is done sending calculations through the pipeline, it stores that data in cache for programs to access (L1 DCache in the diagram below). In essence, these are the completed cars sitting in the parking lot waiting for transport. Intel processors have one parking lot that may contain a mix of cars and trucks, which reduces efficiency when a shipping company arrives to grab a shipment made exclusively of trucks. The Bulldozer plant has two parking lots, which gives that plant more flexibility to be efficient with storing and shipping.

 

From end to end, the entire Bulldozer plant can do more, and do it more intelligently than the plants AMD and Intel run today.

Posted Image

Going back to raw architecture, both of Bulldozer’s lines share a single floating point scheduler (cordoned in red), with two 128-bit FMAC pipelines. Fused multiply-accumulate (FMAC) gives the chip improved floating point precision, which grants Bulldozer a leg up on the Phenom II when it comes to calculating big equations more accurately and efficiently. And, when you realize that everything you do on a computer is a mathematical equation, you can see why this is important.

 

A 128-bit floating point pipe is also a natural choice as AMD has announced SSE5 for the Bulldozer, an instruction extension that has several 128-bit multimedia instructions. Fusing the 128-bit FPUs will also allow the chip to crunch 256-bit Intel AVX instructions in just one cycle. SSE5 and AVX alone will take these processors to a whole new level of performance when it comes to multimedia, encryption and scientific research.

 

Finally, the Bulldozer brings forward the Phenom II’s cache hierarchy by dumping all the pipelines into shared pools of L2 and L3 cache. These shared L2 and L3 caches give either core on a Bulldozer module access to completed calculations that can be pulled back in to speed up a new task. This is standard for today’s processors.

 

Your future Bulldozer CPU

 

The first enthusiast CPU to employ the Bulldozer design is currently codenamed Zambezi, and it will contain four of these dual core modules for a total of eight cores. We also know for a fact that Zambezi will use socket AM3, meaning anyone with a DDR3 Phenom II motherboard will be ready to rock with a BIOS upgrade.

 

What about performance?

 

Unfortunately, there are some elements of the Bulldozer design that we just don’t understand yet, including:

 

* How many cars the supervisor can send down the line at a time;

* How many stages it takes to complete a car;

* How AMD has configured the floating point unit (FPU) to run the numbers;

* and how exactly AMD shares the single FPU amongst two independent assembly lines.

 

Until this information tips up, we just can’t know how Bulldozer will compare to today’s processors. In the interim, we can only admire the genuinely different architecture and speculate over the diagram’s many ambiguities.

 

Bobcat: The chip for netbooks

 

Next on the launch deck is AMD’s “Bobcat” architecture, a chip explicitly designed to cater to products containing CPUs like the Athlon Neo or the Intel Atom. According to the company’s roadmaps, the first chip to launch with Bobcat architecture will be the 32nm Ontario APU, which combines two Bobcat modules and a rudimentary DirectX 11 chip on the same processor.

Posted Image

Each Bobcat module is a single core design, with one supervisor (int scheduler) and one assembly line, which consists of the I-Pipes, Ld-Pipe and St-pipe in the diagram above. These can be considered specialized workers—electricians versus mechanics, for example—that perform unique tasks on the car while it is rolling down the line. You’ll note that Bulldozer, too, had four pipelines per int scheduler, but we just don’t know what kind of workers they are yet.

 

The Bobcat’s integer pipe is paired with a dual-pipe FPU, ambiguously titled “A-Pipe” and “M-Pipe” in this diagram. We postulate that the “A” and “M” refer to the addition and multiplication/division floating point operations, respectively. The size of these pipelines—the number of bits they can calculate at a time—will not only determine what this processor is strongest at, but its complexity, and how it consumes power.

 

On the topic of power, AMD claims that Bobcat is capable of radiating less than 1 watt of heat, which could mean something around 0.5W. A chip at that wattage isn’t doing much more than sitting around on standby, but it’s a healthy number for users looking for laptop designs with a long standby life. In practice, Bobcat’s actual TDP should be around 5-10W, which is perfect for netbook-sized laptops.

 

On the point of performance, AMD says it’ll weigh in at “90% of today’s mainstream performance” at less than half of the die size. If AMD’s definition of mainstream is the Athlon II—an assumption that bears out in their platform roadmaps—then Bobcat is essentially an Athlon II in a (much) smaller, cooler and quieter package. Not bad.

 

Bobcat’s most remarkable feature is not its architecture, however, but its design process. AMD has designed the Bobcat via high-level synthesis, or HLS. HLS is a process by which a chip’s design begins its life as a set of behaviors coded by a programmer in C++. The code is then interpreted and synthesized by a machine that manufactures a processor that exhibits the behavior written by the programmer.

 

HLS is a fascinating way to rapidly design and produce a chip that can easily be modified or ported to other processes for outstanding flexibility in the market. The trade off for this agility is frequency—Bobcat’s maximum clockspeed with an HLS-driven design is about 20% lower than it could have been were it designed “by hand.”

 

All things considered, Bobcat will assuredly be faster than any ultra low-voltage chip in the market today; it will handily eclipse the Nano, the Atom and the Athlon Neo, by orders of magnitude on some metrics. Additionally, AMD’s decision to roll with HLS gives the firm the ability to respond to market conditions in ways its competitors simply cannot with current processes.

 

Fusion: The chip for notebooks and budget desktops

AMD’s acquisition of ATI Technologies was completed on October 26, 2006 and was accompanied by an official, and very important statement:

 

AMD plans to create a new class of x86 processor that integrates the central processing unit (CPU) and graphics processing unit (GPU) at the silicon level with a broad set of design initiatives collectively codenamed “Fusion.”

 

In other words, AMD announced that it would soon put GPUs and CPUs on a processor. AMD calls these chips an accelerated processor unit, or APU. If you’re familiar with the CPU market, the APU might not be new to you: some of Intel’s Core i5 processors have a GPU onboard. Yes, Intel beat AMD to the punch, and it was almost a direct result of AMD’s financial hardship.

 

Despite yielding the first design wins to its chief rival, there is a silver lining for AMD’s APU initiative: even AMD’s slowest modern GPU bloody annihilates anything Intel has to offer. This includes the GPUs AMD plans to stick inside its processors, starting next year with Llano.

 

Llano

The Llano CPU is AMD’s first processor scheduled to adopt the Fusion APU design. Based on the die shots provided earlier this year, the chip strongly resembles an Athlon II X4 that has been shrunk from 45nm to 32nm to accommodate an onboard GPU.

 

This would make perfect sense given that Llano and Propus are both oriented for the mainstream. Marrying existing technologies manufactured at a smaller size is much easier than starting over with a brand new architecture when none is needed.

Posted Image

It is certainly worth noting that the above x-ray of the Llano is not complete; the bottom section of the chip has been cut off in press materials, meaning there’s even more silicon at play than we can see at this time.

 

However, judging from what we can see, the Llano APU will feature 512k-1MB L2 cache per core, no L3 cache and six Radeon HD 5000-series units for a total of 480 stream processors.

 

In short, Llano is shaping up to be an Athlon II X4 with 66% of a Radeon HD 5750 on board. If that bears out, then it is more than capable slugging Intel’s Clarkdale and Arrandale (Core i5) designs into the pavement without lifting much more than a few fingers.

 

Recap

Before we head into our final thoughts, let’s take a moment to quickly summarize all the architectures that have been tossed around in this article.

 

Zambezi

Family: Bulldozer

Cores: 4 to 8

Process: 32nm

Socket: AM3

Onboard GPU?: No

Platform: Scorpius

Role: Performance Desktop

Launch date: Late 2010

 

Ontario

Family: Bobcat

Cores: 2-4

Process: 32nm

Socket: N/A

Onboard GPU?: Yes

Platform: Brazos

Role: Ultra Thins, Netbooks

Launch date: 2011

 

Llano

Family: Stars (Athlon II)

Cores: 4

Process: 32nm

Socket: N/A (AM3 rumored)

Onboard GPU?: Yes

Platform: Brazos

Role: Mainstream notebook, mainstream desktop

Launch date: 2011

 

Final thoughts

AMD has been saying that “the future is Fusion” for years, and the company is just now in a place with its capital and processes to realize that future. By 2011, AMD will completely revamp their desktop, laptop and netbook offerings with three innovative and purpose-built CPU designs, all of which can be paired with on-die GPUs if the market demands it.

 

You read that right: Llano isn’t the only design that can support an onboard GPU. AMD can pair Bulldozer and Bobcat modules with a GPU, too.

 

Now, AMD’s first generation Fusion won’t have the performance to take on the discrete GPU market, but the groundwork is being laid. It will start with mainstream and low-voltage in laptops and netbooks, respectively. Economical desktop designs aren’t out of the question either, but there are signs that something much bigger is in the works.

 

For example, Bulldozer may not be an APU now, but its relatively small floating point unit speaks to a future architecture that cedes floating point operations entirely to the GPU, a component that crushes the CPU in floating point performance.

 

And indeed, in conversations with AMD, this is the paradigm they have been working to kickstart: a computing ecosystem that recognizes CPUs and GPUs alike as valid processors for a program. They envision a day when processing tasks are easily and automatically sent to the best processor for the job.

 

We are just beginning on that road, the one that blurs the line between the CPU and the video card, but AMD appears poised to make a confident first step. They have the resources, they have the engineers, and they have the drive. AMD is extremely passionate about where they’re going with their market strategy; talking to engineers and representatives at all levels of the company reveals an infectious enthusiasm that can’t be manufactured or faked.

 

Do not believe for a moment that competition between AMD and Intel has waned: 2011 will be more exciting than ever."

 

It seems these guys have visited AMD... and have got all caught up in the excitement. But I will just say that the GPU's in some of the i3's when overclocked are as good as an HD4200... which aint bad. Thanks for reading this by the way, I just thought that this could clear up people's questions about what the hell AMD is up to.

 

So now you know. And again, apologies for the wall of text.

 

-SC

Edited by SceptreCore

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Sandy Bridge is going to own this shit

 

 

 

:P

Hehe... it's going to keep many nerds waiting with baited breath. I'm just glad to have found such a comprehensive article.

 

edit: Oh and I will have drop in upgradeablility with Bulldozer... and you will have to buy a new board for sandy bridge so nerrrr! (Doesn't matter though if you have sold all of your parts.)

Edited by SceptreCore

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The best thing about bulldozer is its AM3 compatible, grab a hex core for $250 now then drop a bulldozer in it 12 months later, win win.

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The best thing about bulldozer is its AM3 compatible, grab a hex core for $250 now then drop a bulldozer in it 12 months later, win win.

When you think about it, the compatibility track isn't just cheaper for us... It's cheaper for them too. They don't have to make different sized chips to fit socket/chipset/compatibility. It's just socket. Giving us a wider choice.

 

Intel is going overboard with different sockets.

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Intel is going overboard with different sockets.

 

 

Having 2 current in life sockets. Holy shit I'm confused.

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Intel is going overboard with different sockets.

 

 

Having 2 current in life sockets. Holy shit I'm confused.

 

omgzors your right i7 860 and i7 930 look the same but confuse the fuck outa me cause of different sockets.

 

:P

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Intel is going overboard with different sockets.

Having 2 current in life sockets. Holy shit I'm confused.

 

Soon to be 3. Then 4.

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meh.

I've already had 18 months out of my current CPU

I reckon it's good for another 18 months....at least

I'll be upgrading the graphics....when it starts to feel slow.

right now, the only thing that shits me about my rig, is that I've got it more or less how I want it.....it's kinda boring, but there's nothing out there to entice me to spend money.....the SSD was the final improvement, anything else would be a waste of money, I wouldn't notice any difference ('cept in benchies)

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Well maybe in the next 6-7 months there will be something to entice you?

 

Or maybe some rich foreign relative you never knew you had will kick, and you can grab a 980X.

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Well maybe in the next 6-7 months there will be something to entice you?

 

Or maybe some rich foreign relative you never knew you had will kick, and you can grab a 980X.

 

 

sounds good!

I could live with that.

:)

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Well maybe in the next 6-7 months there will be something to entice you?

 

Or maybe some rich foreign relative you never knew you had will kick, and you can grab a Buldozer Zambezi CPU.

 

 

sounds good!

I could live with that.

:)

 

Heh.

 

Alright enough derailing, back to bulldozer.

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Interesting info about CMT. Could have sworn when the first phenoms came out they were like advertising in a similar fashion -> "instead of intel's dual-dualcore design of a quad, we're making real quads and will offer better multitasking performance blabla"

 

A relief to know they will breathe more life in to AM3 sockets, otherwise what a waste that would have been. I got a spare gigabyte ma78lmt s2, was about to sell it but may end up holding on to it if it can support the upcoming bulldozer. Performance wise, I bet ya their quads will only be equivalent to Lynnfield _finally_ (i.e. i5 750, which is already replaced :P) even then i'm skeptical.

 

either way kudos to AMD.

 

edit: hey look at that im an apprentice, who am i apprenticed to? :P

Edited by alkahest

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Apparently Bulldozer will have a tiny 16KB L1 cache... instead of the usual 64KB. And 2MB L2 cache.Link

 

So far the file contains some details about Bulldozer's cache sizes and associativities:

 

case TARGET_orochi:
	L[0] = MHD_LEVEL(MHD_TYPE_CACHE,	// Type
					 16*1024,		   // Size
					 64,				// Line Size
					 18,				// Clean Miss Penalty
					 18,				// Dirty Miss Penalty
					 4,				 // Associativity
...
	break;


and:



 case TARGET_orochi:
	// TODO: this might be too generous: in multiple processor situations,
	// there is a cost to loading the shared bus/memory.
	L[1] = MHD_LEVEL(MHD_TYPE_CACHE,
					 2*1024*1024, // cache size
					 64,  // cache line size
					 150,
					 200, // ?
					 16,  // associativity
...
	break;
So it looks like one core in a Bulldozer module will have a 4-way set associative 16 kB L1 data cache and the module itself might contain a shared 2 MB L2 cache, with 16-way set associativity, as known from current designs. The miss penalty numbers indicate a higher latency for the L2 cache of 18 cycles.

 

The small L1 cache reminds me of the small L1 caches of Prescott, which later had the same size but twice the associativity. This fact and a lot of indications let me believe, that Bulldozer will be a very different design, where the designers might have traded area and static power consumption for higher dynamic power caused by shorter clock cycle times as a design goal. More on that later.

 

Associativity definition by wikipedia: Associativity is a trade-off. If there are ten places the replacement policy can put a new cache entry, then when the cache is checked for a hit, all ten places must be searched. Checking more places takes more power, chip area, and potentially time. On the other hand, caches with more associativity suffer fewer misses (see conflict misses, below), so that the CPU spends less time servicing those misses. The rule of thumb is that doubling the associativity, from direct mapped to 2-way, or from 2-way to 4-way, has about the same effect on hit rate as doubling the cache size. Associativity increases beyond 4-way have much less effect on the hit rate, and are generally done for other reasons.

 

Cache misses by wikipedia: A cache miss refers to a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency. There are three kinds of cache misses: instruction read miss, data read miss, and data write miss.

- A cache read miss from an instruction cache generally causes the most delay, because the processor, or at least the thread of execution, has to wait (stall) until the instruction is fetched from main memory.

- A cache read miss from a data cache usually causes less delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution.

- A cache write miss to a data cache generally causes the least delay, because the write can be queued and there are few limitations on the execution of subsequent instructions. The processor can continue until the queue is full.

 

Looks like AMD is going all out on Bulldozer, like they're gearing up for a final showdown or something.

 

Interesting info about CMT. Could have sworn when the first phenoms came out they were like advertising in a similar fashion -> "instead of intel's dual-dualcore design of a quad, we're making real quads and will offer better multitasking performance blabla"

 

A relief to know they will breathe more life in to AM3 sockets, otherwise what a waste that would have been. I got a spare gigabyte ma78lmt s2, was about to sell it but may end up holding on to it if it can support the upcoming bulldozer. Performance wise, I bet ya their quads will only be equivalent to Lynnfield _finally_ (i.e. i5 750, which is already replaced :P) even then i'm skeptical.

 

either way kudos to AMD.

 

edit: hey look at that im an apprentice, who am i apprenticed to? :P

You're apprenticed to the entire community... you're now our bitch. :P

 

And what your talking about was something completely different. They were talking about True quad core, which is 4 cores on the one die, not two dual cores etched together. AMD got talked into it by software devs... but unfortunately they were not prepared to pull it off. It was better in a sense that it didn't have to hop over to the other die... but they stuffed up the core design. CMT is something else entirely.

Edited by SceptreCore

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And what your talking about was something completely different. They were talking about True quad core, which is 4 cores on the one die, not two dual cores etched together. AMD got talked into it by software devs... but unfortunately they were not prepared to pull it off. It was better in a sense that it didn't have to hop over to the other die... but they stuffed up the core design. CMT is something else entirely.

umm. I know that. but im talking about AMD building up the hype, once more. Edited by alkahest

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umm. I know that. but im talking about AMD building up the hype, once more.

It's the www that's building up the hype.

 

It also might be good to edit your post, take out all the unnecessary text.

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fixed that and *sigh* nevermind it seems you're missing the point.

No I got your point. Your saying AMD might be building up hype for something of not much chop. But they haven't said anything like that, it's all these tech journos doing research into it that are.

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ah right, fair enough.

 

either way i hope they're right, intel needs some real competition. their prices suck :P

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I worry about AMD's brand recognition at the moment Intel is leaps and bounds ahead in the CPU war at the moment and people tend to be loyal to their brand even if AMD is competitive in the next gen in terms of performance I feel like they will need sustained competitiveness throughout multiple generations to get back to where they used to be in the CPU stakes.

But yea good competition never hurts the consumer in the hip pocket so I hope they are on a winner with this.

Edited by Bundy

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I worry about AMD's brand recognition at the moment Intel is leaps and bounds ahead in the CPU war at the moment and people tend to be loyal to their brand even if AMD is competitive in the next gen in terms of performance I feel like they will need sustained competitiveness throughout multiple generations to get back to where they used to be in the CPU stakes.

But yea good competition never hurts the consumer in the hip pocket so I hope they are on a winner with this.

If you look at the way AMD has been going from strength to strength lately, Bulldozer is just the ground work for a turn around in their CPU department.

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Time for an update: Bulldozer will be Version 1

 

Don't know if anyone has heard of Dresdenboy, but he is usually the guy who digs up the latest scoop of Bulldozer, and anything coming out of AMD pretty much. So kudos to him and his efforts to provide us commoners on the latest.

 

As this posting to the gcc mailing list suggests, the Bulldozer we'll likely see to hit the shelfes in 2011, will be version 1 of the architecture, as indicated by the new tags "bdver1" or "TARGET_BDVER1". So as some already expected, already patented features like speculative multithreading might come with a later version of the microarchitecture.

 

There is a lot of interesting stuff to find in the posted patch. It seems that a lot of numbers (for example costs of instructions) are the same as for K10 in most cases (looks like copy-paste), while the most important changes are described at the beginning:

 

"This patch defines -march=bdver1 and -mtune=bdver1 flag for the upcoming

AMD Bulldozer processor.

 

This patch also implements the following optimizations for Bulldozer

which are different from the previous generation of AMD processor named

AMDFAM10 or Barcelona.

 

- For 128-bit misaligned SSEx stores, use movupx instead of movlpx/movhpx

pairs. For 128-bit misaligned AVX loads and stores use movupx.

128-bit misaligned SSE/AVX stores are not micro-coded on Buldozer

unlike Barcelona.

As a side effect of the above, some instances of array copy/set loops

using integer/scalar FP moves are replaced with SSEx/AVX vector

128-bit moves.

 

- Improve fetch bandwidth by reducing code size.

This is accomplished by:

Replacing "packed double (PD)" and "packed integer (DQ)" forms of some

SSEx/AVX instructions with "packed single (PS)" forms, where the "PS" form

of the instruction is 1 byte shorter than the "PD" or "DQ" form.

This applies to

- use movaps instead of movapd/movdqa.

- use movups instead of movupd/movdqu.

- use xorps/andps/orpd instead of xorpd/andpd/orpd.

 

- Restore SSEx/AVX scalar converts since the scalar converts are not

microded on Bulldozer while they were microded on Barcelona.

This is accomplished by:

1. Not replacing scalar single precision (SP) to double precision (DP)

and DP to SP converts with the corresponding packed versions.

2. Not replacing scalar 32-bit signed integer to SP/DP converts with the

corresponding packed versions.

3. Not replacing memory forms of the above instructions with the reg-reg

form of same instruction.

 

- Exploit opportunities to generate cmp-jmp instructions instead of

inc/dec-jmp instructions since Bulldozer can do cmp/jmp fusion.

 

There are other optimizations that will need to be enhanced for Bulldozer

and more patches will be sent as the work progresses.

 

Correctness and performance testing is yet to be started on the simulator,

but static analysis testing has been done comparing polyhedron benchmarks

assembly listings."

 

I'm not sure if this refers to an engineering sample... or if there is a version two planned already, but it's interesting to note.

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Fascinating article, and very glad to hear my AM3 board still has a lot of life in it.

 

One thing though, that I find scary...

 

" HLS is a process by which a chip’s design begins its life as a set of behaviors coded by a programmer in C++. The code is then interpreted and synthesized by a machine that manufactures a processor that exhibits the behavior written by the programmer."

 

beginnings of Skynet, anyone?

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